82801FB Datasheet, PDF (289/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.1.17
8.1.18
8.1.19
8.1.20
INT_PN — Interrupt Pin Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Dh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
Interrupt Pin (INT_PN) — RO. Hardwired to 01h to indicate that the LAN controller’s interrupt
7:0
request is connected to PIRQA#. However, in the ICH6 implementation, when the LAN controller
interrupt is generated PIRQE# will go active, not PIRQA#. Note that if the PIRQE# signal is used as
a GPI, the external visibility will be lost (though PIRQE# will still go active internally).
MIN_GNT — Minimum Grant Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Eh
Default Value: 08h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Minimum Grant (MIN_GNT) — RO. This field indicates the amount of time (in increments of 0.25 µs)
that the LAN controller needs to retain ownership of the PCI bus when it initiates a transaction.
MAX_LAT — Maximum Latency Register
(LAN Controller—B1:D8:F0)
Offset Address: 3Fh
Default Value: 38h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Maximum Latency (MAX_LAT) — RO. This field defines how often (in increments of 0.25 µs) the
LAN controller needs to access the PCI bus.
CAP_ID — Capability Identification Register
(LAN Controller—B1:D8:F0)
Offset Address: DCh
Default Value: 01h
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Capability ID (CAP_ID) — RO. Hardwired to 01h to indicate that the Intel^® ICH6’s integrated LAN
controller supports PCI power management.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
289