82801FB Datasheet, PDF (427/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.9.6
TCO1_CNT—TCO1 Control Register
I/O Address:
Default Value:
Lockable:
TCOBASE +08h
0000h
No
Attribute:
Size:
Power Well:
R/W, R/W (special), R/WC
16-bit
Core
Bit
Description
15:13 Reserved
TCO_LOCK — R/W (special). When set to 1, this bit prevents writes from changing the TCO_EN bit
12
(in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not be cleared by
software writing a 0 to this bit location. A core-well reset is required to change this bit from 1 to 0.
This bit defaults to 0.
TCO Timer Halt (TCO_TMR_HLT) — R/W.
0 = The TCO Timer is enabled to count.
11 ^{1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will cause an SMI#}
or set the SECOND_TO_STS bit. When set, this bit will prevent rebooting and prevent Alert On
LAN event messages from being transmitted on the SMLINK (but not Alert On LAN* heartbeat
messages).
SEND_NOW — R/W (special).
0 = The ICH6 will clear this bit when it has completed sending the message. Software must not set
this bit to 1 again until the ICH6 has set it back to 0.
10
1 = Writing a 1 to this bit will cause the ICH6 to send an Alert On LAN Event message over the
SMLINK interface, with the Software Event bit set.
Setting the SEND_NOW bit causes the ICH6 integrated LAN controller to reset, which can have
unpredictable side-effects. Unless software protects against these side effects, software should not
attempt to set this bit.
NMI2SMI_EN — R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent upon the
settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the following table:
9
NMI_EN
GBL_SMI_EN
Description
0b
0b
No SMI# at all because GBL_SMI_EN = 0
0b
1b
SMI# will be caused due to NMI events
1b
0b
No SMI# at all because GBL_SMI_EN = 0
1b
1b
No SMI# due to NMI because NMI_EN = 1
NMI_NOW — R/WC.
0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear this bit. Another
8
NMI will not be generated until the bit is cleared.
1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force an entry to
the NMI handler.
7:0 Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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