82801FB Datasheet, PDF (521/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

UHCI Controllers Registers
13.2.3
13.2.4
USBINTR—USB Interrupt Enable Register
I/O Offset:
Default Value:
Base + (04–05h)
0000h
Attribute:
Size:
R/W
16 bits
This register enables and disables reporting of the corresponding interrupt to the software. When a
bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Fatal errors
(host controller processor error, (D29:F0/F1/F2/F3:BASE + 02h, bit 4, USBSTS Register) cannot
be disabled by the host controller. Interrupt sources that are disabled in this register still appear in
the Status Register to allow the software to poll for events.
Bit
Description
15:5 Reserved
4 Scratchpad (SP) — R/W.
Short Packet Interrupt Enable — R/W.
3 _{0 = Disabled.}
1 = Enabled.
Interrupt on Complete Enable (IOC) — R/W.
2 _{0 = Disabled.}
1 = Enabled.
Resume Interrupt Enable — R/W.
1 _{0 = Disabled.}
1 = Enabled.
Timeout/CRC Interrupt Enable — R/W.
0 _{0 = Disabled.}
1 = Enabled.
FRNUM—Frame Number Register
I/O Offset:
Default Value:
Base + (06–07h)
0000h
Attribute: R/W (Writes must be Word Writes)
Size:
16 bits
Bits [10:0] of this register contain the current frame number that is included in the frame SOF
packet. This register reflects the count value of the internal frame number counter. Bits [9:0] are
used to select a particular entry in the Frame List during scheduled execution. This register is
updated at the end of each frame time.
This register must be written as a word. Byte writes are not supported. This register cannot be
written unless the host controller is in the STOPPED state as indicated by the HCHalted bit
(D29:F0/F1/F2/F3:BASE + 02h, bit 5). A write to this register while the Run/Stop bit is set
(D29:F0/F1/F2/F3:BASE + 00h, bit 0) is ignored.
Bit
15:11
10:0
Description
Reserved
Frame List Current Index/Frame Number — R/W. This field provides the frame number in the
SOF Frame. The value in this register increments at the end of each time frame (approximately
every 1 ms). In addition, bits [9:0] are used for the Frame List current index and correspond to
memory address signals [11:2].
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
521