82801FB Datasheet, PDF (159/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.14.6.2
5.14.6.3
5.14.6.4
5.14.6.5
Behavioral Description
• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH6 de-asserts
(drive high) CLKRUN# for 1 clock and then tri-states the signal.
Conditions for Maintaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the
CLKRUN# signal de-asserted, and then must re-assert if (drive it low) within 3 clocks.
• When the ICH6 has tri-stated the CLKRUN# signal after de-asserting it, the ICH6 then checks
to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the ICH6 again starts asserting the
signal.
• If an internal device needs the PCI bus, the ICH6 asserts the CLKRUN# signal.
Conditions for Stopping the PCI Clock
• If no device re-asserts CLKRUN# once it has been de-asserted for at least 6 clocks, the ICH6
stops the PCI clock by asserting the STP_PCI# signal to the clock synthesizer.
Conditions for Re-Starting the PCI Clock
• A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
• When the ICH6 observes the CLKRUN# signal asserted for 1 (free running) clock, the ICH6
de-asserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH6 again
starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the ICH6 re-asserts CLKRUN#, and
simultaneously de-asserts the STP_PCI# signal.
LPC Devices and CLKRUN#
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC serial
interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles
will not need to assert CLKRUN#, since the ICH6 asserts it on their behalf.
The LDRQ# inputs are ignored by the ICH6 when the PCI clock is stopped to the LPC devices in
order to avoid misinterpreting the request. The ICH6 assumes that only one more rising PCI clock
edge occurs at the LPC device after the assertion of STP_PCI#. Upon de-assertion of STP_PCI#,
the ICH6 assumes that the LPC device receives its first clock rising edge corresponding to the
ICH6’s second PCI clock rising edge after the de-assertion.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
159