82801FB Datasheet, PDF (485/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.2.2
12.2.3
BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
Address Offset:
Default Value:
Primary: BAR + 02h
Secondary: BAR + 0Ah
00h
Attribute: R/W, R/WC, RO
Size:
8 bits
Bit
Description
PRD Interrupt Status (PRDIS) — R/WC.
7 _{0 = Software clears this bit by writing a 1 to it.}
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set.
Drive 1 DMA Capable — R/W.
0 = Not Capable.
6 ^{1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this}
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The Intel^® ICH6 does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
Drive 0 DMA Capable — R/W.
0 = Not Capable
5 ^{1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this}
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH6 does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
4:3 Reserved. Returns 0.
Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
2 _{1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not disabled}
interrupts via the nIEN bit of the Device Control Register (see chapter 5 of the Serial ATA
Specification, Revision 1.0a).
Error — R/WC.
1 ^{0 = Software clears this bit by writing a 1 to it.}
1 = This bit is set when the controller encounters a target abort or master abort when transferring
data on PCI.
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH6 when the last transfer for a region is performed, where EOT for
that region is set in the region descriptor. It is also cleared by the ICH6 when the Start Bus
0
Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read
as a 0, all data transferred from the drive during the previous bus master command is visible in
system memory, unless the bus master command was aborted.
1 = Set by the ICH6 when the Start bit is written to the Command register.
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)
Address Offset:
Default Value:
Primary: BAR + 04h–07h
Attribute:
Secondary: BAR + 0Ch–0Fh
All bits undefined
Size:
R/W
32 bits
Bit
Description
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to A[31:2]. The
31:2 Descriptor Table must be dword-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
1:0 Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
485