82801FB Datasheet, PDF (74/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-21. Power and Ground Signals (Sheet 2 of 2)
Name
Description
VccSATAPLL
V_CPU_IO
Vss
1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL. This power
may be shut off in S3, S4, S5 or G3 states. Must be powered even if SATA not used.
Powered by the same supply as the processor I/O voltage (3 pins). This supply is used to
drive the processor interface signals listed in Table 2-13.
Grounds (172 pins).
2.22 Pin Straps
2.22.1 Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of
PWROK to select configurations (except as noted), and then revert later to their normal usage. To
invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it
is sampled.
Table 2-22. Functional Strap Definitions (Sheet 1 of 2)
Signal
Usage
When Sampled
Comment
GNT[6]#/
GPO[16]
Top-Block
Swap
Override
LINKALERT# Reserved
SPKR
No Reboot
INTVRMEN
GPIO[25]
Integrated
VccSus1_5
VRM Enable/
Disable
Integrated
Vcc2_5 VRM
Enable/
Disable
EE_CS
Reserved
Rising Edge of
PWROK
Rising Edge of
PWROK
Always
Rising Edge of
RSMRST#
The signal has a weak internal pull-up. If the signal is
sampled low, this indicates that the system is strapped to
the “top-block swap” mode (ICH6 inverts A16 for all cycles
targeting FWH BIOS space). The status of this strap is
readable via the Top Swap bit (Chipset Configuration
Registers:Offset 3414h:bit 0). Note that software will not be
able to clear the Top-Swap bit until the system is rebooted
without GNT6# being pulled down.
This signal requires an external pull-up resistor.
The signal has a weak internal pull-down. If the signal is
sampled high, this indicates that the system is strapped to
the “No Reboot” mode (ICH6 will disable the TCO Timer
system reboot feature). The status of this strap is readable
via the NO REBOOT bit (Chipset Configuration
Registers:Offset 3410h:bit 5).
This signal enables integrated VccSus1_5 VRM when
sampled high.
This signal enables integrated Vcc2_5 VRM when sampled
low. This signal has a weak internal pull-up during
RSMRST# and is disabled within 100 ms after RSMRST#
de-asserts.
This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high.
74
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet