82801FB Datasheet, PDF (72/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-20. General Purpose I/O Signals^1,2 (Sheet 2 of 2)
Name
Type Tolerance Power Well
Description
GPO[18]
O
(Desktop Only)
GPO[17]
O
GPO[16]
O
GPI[15:14]³
I
GPI[13]³
I
GPI[12]³
I
GPI[11]³
I
GPI[10:9]³
I
GPI[8]³
I
GPI[7]³
I
GPI[6]³
I
(Desktop Only)
GPI[5:2]³
I
GPI[1:0]³
I
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
5V
5V
Core
Core
Core
Resume
Resume
Core
Resume
Resume
Resume
Core
Core
Core
Core
This signal is fixed as output only. In mobile
configurations this GPO is not implemented and is
used instead as STP_PCI#.
NOTE: GPO[18] will blink by default immediately after
reset (controllable by GPO_BLINK
(D31:F0:Offset GPIOBASE+18h:bit 18)).
This signal is fixed as output only and can be used
instead as PCI GNT[5]#.
This signal is fixed as output only and can be used
instead as PCI GNT[6]#.
This signal is fixed as input only and can be used
instead as OC[7:6]#
This signal is fixed as input only and is unmultiplexed.
This signal is fixed as input only and is unmultiplexed.
This signal is fixed as input only and can be used
instead as SMBALERT#.
This signal is fixed as input only and can be used
instead as OC[5:4]#.
This signal is fixed as input only and is unmultiplexed.
This signal is fixed as input only and is unmultiplexed.
This signal is fixed as input only. In mobile this GPI is
not implemented and is used instead as BMBUSY#.
This signal is fixed as input only and can be used
instead as PIRQ[H:E]#.
This signal is fixed as input only and can be used
instead as PCI REQ[6:5]#.
NOTES:
1. All inputs are sticky. The status bit remains set as long as the input was asserted for two clocks. GPIs are
sampled on PCI clocks in S0/S1 for desktop and S0 for mobile configurations. GPIs are sampled on RTC
clocks in S3/S4/S5 for desktop and S1/S3/S4/S5 in mobile configurations.
2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not
driven high into powered-down planes. Some ICH6 GPIOs may be connected to pins on devices that exist in
the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a
Power Button Override event will result in the Intel ICH6 driving a pin to a logic 1 to another device that is
powered down.
3. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an
SCI, but not both.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet