82801FB Datasheet, PDF (122/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.6.1
5.6.1.1
5.6.1.2
5.6.2
Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and
channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA
Command Register.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a
software request for DMA service can be presented through each channel's DMA Request Register.
A software request is subject to the same prioritization as any hardware request. See the detailed
register description for Request Register programming information in Section 10.2.
Fixed Priority
The initial fixed priority structure is as follows:
High priority
0, 1, 2, 3
Low priority
5, 6, 7
The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the highest
priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority
position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7.
Rotating Priority
Rotation allows for "fairness" in priority resolution. The priority chain rotates so that the last
channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).
Channels 0–3 rotate as a group of 4. They are always placed between channel 5 and channel 7 in
the priority list.
Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in
the rotation, while channel group (0–3) comprises the fourth position in the arbitration.
Address Compatibility Mode
When the DMA is operating, the addresses do not increment or decrement through the High and
Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address is
010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next address
is 02FFFFh, not 01FFFFh. However, when the DMA is operating in 16-bit mode, the addresses still
do not increment or decrement through the High and Low Page Registers but the page boundary is
now 128 K. Therefore, if a 24-bit address is 01FFFEh and increments, the next address is 000000h,
not 0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is
03FFFEh, not 02FFFEh. This is compatible with the 82C37 and Page Register implementation
used in the PC-AT. This mode is set after CPURST is valid.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet