82801FB Datasheet, PDF (467/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.22 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
Address Offset: 44h
Default Value: 00h
Attribute: R/W
Size:
8 bits
Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when
the PCI functions are combined. These bits have no effect on SATA operation unless otherwise
noted.
Bit
Description
Secondary Drive 1 IORDY Sample Point (SISP1) — R/W. This field determines the number of PCI
clocks between IDE IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive
1 data port and bit 14 of the IDE timing register for secondary is set.
7:6 ^{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Secondary Drive 1 Recovery Time (SRCT1) — R/W. This field determines the minimum number of
PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the
access is to drive 1 data port and bit 14 of the IDE timing register for secondary is set.
5:4 ^{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Primary Drive 1 IORDY Sample Point (PISP1) — R/W. This field determines the number of PCI
clocks between IOR#/IOW# assertion and the first IORDY sample point, if the access is to drive 1
data port and bit 14 of the IDE timing register for primary is set.
3:2 ^{00 = 5 clocks}
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Primary Drive 1 Recovery Time (PRCT1) — R/W. This field determines the minimum number of
PCI clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle, if the
access is to drive 1 data port and bit 14 of the IDE timing register for primary is set.
1:0 ^{00 = 4 clocks}
01 = 3 clocks
10 = 2 clocks
11 = 1 clocks
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
467