82801FB Datasheet, PDF (780/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Testability
Figure 24-2. Example XOR Chain Circuitry
Vcc
Input
Pin 1
Input
Pin 2
Input
Pin 3
Input
Pin 4
Input
Pin 5
Input
Pin 6
XOR
Chain
Output
24.1.1 XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity
(e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in Table 24-1.
Table 24-1. XOR Test Pattern Example
Vector
1
2
3
4
5
6
7
Input
Pin 1
0
1
1
1
1
1
1
Input
Pin 2
0
0
1
1
1
1
1
Input
Pin 3
0
0
0
1
1
1
1
Input
Pin 4
0
0
0
0
1
1
1
Input
Pin 5
0
0
0
0
0
1
1
Input
Pin 6
0
0
0
0
0
0
1
XOR
Output
1
0
1
0
1
0
1
In this example, Vector 1 applies all 0’s to the chain inputs. The outputs being non-inverting will
consistently produce a 1 at the XOR output on a good board. One short to VCC (or open floating to
VCC) will result in a 0 at the chain output, signaling a defect.
Likewise, applying Vector 7 (all 1’s) to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a 1 at the XOR chain output on a good board.
One short to VSS (or open floating to VSS) will result in a 0 at the chain output, signaling a defect.
It is important to note that the number of inputs pulled to 1 will affect the expected chain output
value. If the number of chain inputs pulled to 1 is even, then expect 1 at the output. If the number of
chain inputs pulled to 1 is odd, expect 0 at the output.
Continuing with the example in Table 24-1, as the input pins are driven to 1 across the chain in
sequence, the XOR Output will toggle between 0 and 1. Any break in the toggling sequence (e.g.,
“1011”) will identify the location of the short or open.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet