82801FB Datasheet, PDF (131/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.9
8259 Interrupt Controllers (PIC) (D31:F0)
The ICH6 incorporates the functionality of two 8259 interrupt controllers that provide system
interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard
controller, serial ports, parallel ports, floppy disk, IDE, mouse, and DMA channels. In addition,
this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the
compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0–7. Table 5-12
shows how the cores are connected.
.
Table 5-12. Interrupt Controller Core Connections
8259
Master
Slave
8259
Input
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Typical Interrupt
Source
Connected Pin / Function
Internal
Keyboard
Internal Timer / Counter 0 output / HPET #0
IRQ1 via SERIRQ
Internal
Serial Port A
Slave controller INTR output
IRQ3 via SERIRQ, PIRQ#
Serial Port B
IRQ4 via SERIRQ, PIRQ#
Parallel Port / Generic
Floppy Disk
IRQ5 via SERIRQ, PIRQ#
IRQ6 via SERIRQ, PIRQ#
Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#
Internal Real Time Clock Internal RTC / HPET #1
Generic
IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
Generic
Generic
IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
IRQ11 via SERIRQ, SCI, TCO, or PIRQ#
PS/2 Mouse
Internal
IDE cable, SATA
IRQ12 via SERIRQ, SCI, TCO, or PIRQ#
State Machine output based on processor FERR#
assertion. May optionally be used for SCI or TCO interrupt
if FERR# not needed.
IDEIRQ (legacy mode, non-combined or combined
mapped as primary), SATA Primary (legacy mode), or via
SERIRQ or PIRQ#
IDE cable, SATA
IDEIRQ (legacy mode — combined, mapped as
secondary), SATA Secondary (legacy mode) or via
SERIRQ or PIRQ#
The ICH6 cascades the slave controller onto the master controller through master controller
interrupt input 2. This means there are only 15 possible interrupts for the ICH6 PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and
IRQ13.
Note:
Active-low interrupt sources (e.g., the PIRQ#s) are inverted inside the ICH6. In the following
descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface
of the 8259s, after the required inversions have occurred. Therefore, the term “high” indicates
“active,” which means “low” on an originating PIRQ#.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
131