82801FB Datasheet, PDF (716/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

High Precision Event Timer Registers
20.1 Memory Mapped Registers
Table 20-1. Memory-Mapped Registers
Offset
Mnemonic
Register
000–007h
008–00Fh
010–017h
018–01Fh
GCAP_ID General Capabilities and Identification
—
GEN_CONF
—
Reserved
General Configuration
Reserved
020–027h GINTR_STA General Interrupt Status
028–0EFh
0F0–0F7h
0F8–0FFh
100–107h
108–10Fh
110–11Fh
120–127h
128–12Fh
130–13Fh
140–147h
148–14Fh
150–15Fh
160–3FFh
—
MAIN_CNT
—
TIM0_CONF
TIM0_COMP
—
TIM1_CONF
TIM1_COMP
—
TIM2_CONF
TIM2_COMP
—
—
Reserved
Main Counter Value
Reserved
Timer 0 Configuration and Capabilities
Timer 0 Comparator Value
Reserved
Timer 1 Configuration and Capabilities
Timer 1 Comparator Value
Reserved
Timer 2 Configuration and Capabilities
Timer 2 Comparator Value
Reserved
Reserved
Default
Type
0429B17F80
86A201h
RO
—
—
0000h
R/W
—
00000000
00000000h
—
—
R/WC, R/W
—
N/A
R/W
—
—
N/A
R/W, RO
N/A
R/W
—
—
N/A
R/W, RO
N/A
R/W
—
—
N/A
R/W, RO
N/A
R/W
—
—
—
—
NOTES:
1. Reads to reserved registers or bits will return a value of 0.
2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision Event Timers. If
attempted, the lock is not honored, which means potential deadlock conditions may occur.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet