82801FB Datasheet, PDF (202/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.20.1.3
EHC Resets
In addition to the standard ICH6 hardware resets, portions of the EHC are reset by the HCRESET
bit and the transition from the D3_HOT device power management state to the D0 state. The effects
of each of these resets are shown in the following table:
Reset
HCRESET bit set.
Does Reset
Does not Reset
Memory space registers
except Structural
Parameters (which is
written by BIOS).
Configuration
registers.
Software writes the
Device Power State
from D3_HOT (11b) to
D0 (00b).
Core well registers
(except BIOS-
programmed registers).
Suspend well
registers; BIOS-
programmed core
well registers.
Comments
The HCRESET must only affect
registers that the EHCI driver
controls. PCI Configuration space
and BIOS-programmed parameters
can not be reset.
The D3-to-D0 transition must not
cause wake information (suspend
well) to be lost. It also must not clear
BIOS-programmed registers
because BIOS may not be invoked
following the D3-to-D0 transition.
If the detailed register descriptions give exceptions to these rules, those exceptions override these
rules. This summary is provided to help explain the reasons for the reset policies.
5.20.2
Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 for details.
5.20.3
USB 2.0 Enhanced Host Controller DMA
The ICH6 USB 2.0 EHC implements three sources of USB packets. They are, in order of priority
on USB during each microframe:
1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port),
2. The Periodic DMA engine, and
3. The Asynchronous DMA engine. The ICH6 always performs any currently-pending debug
port transaction at the beginning of a microframe, followed by any pending periodic traffic for
the current microframe. If there is time left in the microframe, then the EHC performs any
pending asynchronous traffic until the end of the microframe (EOF1). Note that the debug port
traffic is only presented on one port (Port #0), while the other ports are idle during this time.
5.20.4
Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
5.20.5
Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet