82801FB Datasheet, PDF (499/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
Bit
Description
2 Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1.
Spin-Up Device (SUD) — R/W / RO
This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W when CAP.SSS
(ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support staggered spin-up (when
1 CAP.SSS is 0).
0 = No action.
1 = On an edge detect from 0 to 1, the ICH6 starts a COMRESET initialization sequence to the
device.
Start (ST) — R/W. When set, the ICH6 may process the command list. When cleared, the ICH6 may
not process the command list. Whenever this bit is changed from a 0 to a 1, the ICH6 starts
processing the command list at entry 0. Whenever this bit is changed from a 1 to a 0, the PxCI
0 _{register is cleared by the ICH6 upon the ICH6 putting the controller into an idle state.}
Refer to section 12.2.1 of the Serial ATA AHCI Specification for important restrictions on when ST
can be set to 1.
12.3.2.8
PxTFD—Port [3:0] Task File Data Register (D31:F2)
Address Offset:
Default Value:
Port 0: ABAR + 120h
Attribute:
Port 1: ABAR + 1A0h (Desktop Only)
Port 2: ABAR + 220h
Port 3: ABAR + 2A0h (Desktop Only)
0000007Fh
Size:
RO
32 bits
This is a 32-bit register that copies specific fields of the task file when FISes are received. The
FISes that contain this information are:
D2H Register FIS
PIO Setup FIS
Set Device Bits FIS
Bit
Description
31:16
15:8
Reserved
Error (ERR) — RO. Contains the latest copy of the task file error register.
Status (STS) — RO. Contains the latest copy of the task file status register. Fields of note in this
register that affect AHCI.
Bit
7
7:0
6:4
3
2:1
0
Field
BSY
N/A
DRQ
N/A
ERR
Definition
Indicates the interface is busy
Not applicable
Indicates a data transfer is requested
Not applicable
Indicates an error during the transfer
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
499