82801FB Datasheet, PDF (758/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Electrical Characteristics
Table 22-22. Power Management Timings (Sheet 3 of 3)
Sym
Parameter
t297 SLP_S5# inactive to SLP_S4# inactive
t298 SLP_S4# inactive to SLP_S3# inactive
t299 S4 Wake Event to SLP_S4# inactive (S4 Wake)
t300 S3 Wake Event to SLP_S3# inactive (S3 Wake)
CPUSLP# inactive to STPCLK# inactive
t301
(Desktop Only)
t302
(S3_HOT Configuration Only) SLP_S3# inactive to
ICH6 check for PWROK active
Other Timings
t310
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
Min Max Units
See Note Below
1
2 RTCCLK
See Note Below
small
0
as
possi
RTCCLK
ble
Fig
22-23
22-24
22-25
22-26
22-23
22-24
22-25
22-26
22-23
22-24
22-25
22-26
22-23
22-24
22-25
22-26
Notes
2
3
2
3
8
– PCICLK 22-22
22-23
4
5
msec
22-24
22-25
22-26
–
2 PCI CLK
NOTES:
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
2. The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the
“SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).
3. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
4. Note that this does not apply for synchronous SMIs.
5. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
6. If the (G)MCH does not have the CPUSLP# signal, then the minimum value can be 0 µs.
7. This is a clock generator specification
8. This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert time for
DPRSLPVR has been met, then this is permitted to be 0.
9. This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert time for
STP_CPU# has been met, then this is permitted to be 0.
10.This value should be at most a few clocks greater than the minimum.
11.This value is programmable in multiples of 1024 PCI clocks. Maximum is 8192 PCI clocks (245.6 µs).
12.The ICH6 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
for this cycle getting to the ICH6 is dependant on the processor and the memory controller.
13.The ICH6 has no maximum timing requirement for this transition. It is up to the system designer to determine
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
14.If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
together similar to timing t287 (PCIRST# active to SLP_S3# active).
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet