82801FB Datasheet, PDF (661/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.17
CORBRP—CORB Read Pointer Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 4Ah
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB Read Pointer
to 0 and clear any residual prefetched commands in the CORB hardware buffer within the Intel High
Definition Audio controller. The hardware will physically update this bit to 1 when the CORB Pointer
15 reset is complete. Software must read a 1 to verify that the reset completed correctly. Software must
clear this bit back to 0 and read back the 0 to verify that the clear completed correctly. The CORB
DMA engine must be stopped prior to resetting the Read Pointer or else DMA transfer may be
corrupted.
14:8 Reserved.
CORB Read Pointer — R/W. Software reads this field to determine how many commands it can
write to the CORB without over-running. The value read indicates the CORB Read Pointer offset in
7:0 DWord granularity. The offset entry read from this field has been successfully fetched by the DMA
controller and may be over-written by software. Supports 256 CORB entries (256x4B = 1KB). This
register field may be ready while the DMA engine is running.
18.2.18
CORBCTL—CORB Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 4Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved.
Enable CORB DMA Engine — R/W.
0 = DMA stop
1 ^{1 = DMA run}
After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will
physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from
this bit to verify that the DMA engine is truly stopped.
CORB Memory Error Interrupt Enable — R/W.
0 _{If this bit is set the controller will generate an interrupt if the CMEI status bit (HDBAR + 4Dh: bit 0) is}
set.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
661