82801FB Datasheet, PDF (284/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.1.4
PCISTS—PCI Status Register
(LAN Controller—B1:D8:F0)
Offset Address: 06–07h
Default Value: 0290h
Attribute:
Size:
RO, R/WC
16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15
0 = Parity error Not detected.
1 = The Intel^® ICH6’s integrated LAN controller has detected a parity error on the PCI bus (will be
set even if Parity Error Response is disabled in the PCI Command register).
Signaled System Error (SSE) — R/WC.
14 ^{0 = Integrated LAN controller has not asserted SERR#}
1 = The ICH6’s integrated LAN controller has asserted SERR#. SERR# can be routed to cause
NMI, SMI#, or interrupt.
Master Abort Status (RMA) — R/WC.
13 _{0 = Master Abort not generated}
1 = The ICH6’s integrated LAN controller (as a PCI master) has generated a master abort.
Received Target Abort (RTA) — R/WC.
12 _{0 = Target abort not received.}
1 = The ICH6’s integrated LAN controller (as a PCI master) has received a target abort.
11 Signaled Target Abort (STA) — RO. Hardwired to 0. The device will never signal Target Abort.
DEVSEL# Timing Status (DEV_STS) — RO.
10:9
01h = Medium timing.
Data Parity Error Detected (DPED) — R/WC.
0 = Parity error not detected (conditions below are not met).
8 ^{1 = All of the following three conditions have been met:}
1.The LAN controller is acting as bus master
2.The LAN controller has asserted PERR# (for reads) or detected PERR# asserted (for writes)
3.The Parity Error Response bit in the LAN controller’s PCI Command Register is set.
7
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast back-to-
back transactions.
6 User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66 MHz PCI.
Capabilities List (CAP_LIST) — RO.
4 ^{0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power}
Management.
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management.
3
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from
the state of the Interrupt Enable bit in the command register.
2:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet