82801FB Datasheet, PDF (707/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.53
UES — Uncorrectable Error Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 144–147h
Attribute: R/WC, RO
Default Value: 00000000000x0xxx0x0x0000000x0000bSize:32 bits
This register maintains its state through a platform reset. It loses its state upon suspend.
Bit
Description
31:21 Reserved
20
Unsupported Request Error Status (URE) — R/WC. This bit indicates an unsupported request
was received.
19 ECRC Error Status (EE) — RO. ECRC is not supported.
18 Malformed TLP Status (MT) — R/WC. This bit indicates a malformed TLP was received.
17 Receiver Overflow Status (RO) — R/WC. This bit indicates a receiver overflow occurred.
16
Unexpected Completion Status (UC) — R/WC. This bit indicates an unexpected completion was
received.
15 Completion Abort Status (CA) — R/WC. This bit indicates a completer abort was received.
14 Completion Timeout Status (CT) — R/WC. This bit indicates a completion timed out.
13 Flow Control Protocol Error Status (FCPE) — RO. Flow Control Protocol Errors not supported.
12 Poisoned TLP Status (PT) — R/WC. This bit indicates a poisoned TLP was received.
11:5 Reserved
4
Data Link Protocol Error Status (DLPE) — R/WC. This bit indicates a data link protocol error
occurred.
3:1 Reserved
0 Training Error Status (TE) — RO. Training Errors not supported.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
707