82801FB Datasheet, PDF (649/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.1.49
L1ADDU—Link 1 Upper Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 14Ch
Default Value: See Register Description
Attribute:
Size:
RO
32 bits
Bit
Description
31:0
Link 1 Upper Address — RO. Hardwired to match the RCBA register value in the PCI-LPC bridge
(D31:F0:F0h).
18.2 Intel^® High Definition Audio Memory Mapped
Configuration Registers
(Intel^® High Definition Audio— D27:F0)
The base memory location for these memory mapped configuration registers is specified in the
HDBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The individual registers are then
accessible at HDBAR + Offset as indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Table 18-2. Intel^® High Definition Audio PCI Register Address Map
(Intel^® High Definition Audio
D27:F0) (Sheet 1 of 4)
HDBAR +
Offset
00–01h
02h
03h
04–05h
06–07h
08–0Bh
0C–0Dh
0E–0Fh
10–11h
20–23h
24–27h
30–33h
34–37h
40–43h
44–47h
48–49h
4A–4Bh
4Ch
Mnemonic
Register Name
GCAP
Global Capabilities
VMIN
Minor Version
VMAJ
Major Version
OUTPAY Output Payload Capability
INPAY
Input Payload Capability
GCTL
Global Control
WAKEEN Wake Enable
STATESTS State Change Status
GSTS
Global Status
INTCTL Interrupt Control
INTSTS Interrupt Status
WALCLK Wall Clock Counter
SSYNC Stream Synchronization
CORBLBASE CORB Lower Base Address
CORBUBASE CORB Upper Base Address
CORBWP CORB Write Pointer
CORBRP CORB Read Pointer
CORBCTL CORB Control
Default
4401h
00h
01h
003Ch
001Dh
00000000h
0000h
0000h
0000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
0000h
0000h
00h
Access
RO
RO
RO
RO
RO
R/W
R/W
R/WC
R/WC
R/W
RO
RO
R/W
R/W, RO
R/W
R/W
R/W
R/W
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
649