82801FB Datasheet, PDF (474/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
Bits
Description
1
(Mobile Reserved
Only)
Port 0 Enabled (P0E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
0
1 = Enabled. The port can transition between the on, partial, and slumber states and can detect
devices.
NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1)
12.1.31
.
SIR - SATA Initialization Register
Address Offset: 94h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:28 Reserved
27:24
(Desktop ^Reserved
Only)
27:24
(Mobile
Only)
SATA Initialization Field 3 (SIF3) — R/W. BIOS shall always program this field to the value 0Ah.
All other values are reserved.
23
SATA Initialization Field 2 (SIF2) — R/W. BIOS shall always program this register to the value 1b.
All other values are reserved.
22:10 Reserved
SCR Access Enable (SCRAE) — R/W. In non-AHCI mode, this bit allows access to the SATA
SCR registers (SStatus, SControl, and SError registers).
0 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset 04h:bit 1)
remain as defined.
1 = The ABAR (Dev31:F2:Offset 24h) register and MSE bit field (Dev31:F2:Offset 04h:bit 1) are
forced to be read/write.
9
NOTES:
1. Using this mode only allows access to AHCI registers PxSSTS, PxSCRTL, PxSERR. All other
AHCI space is reserved when this bit is set.
2. Proper use of this bit requires:
• ABAR must be programmed to a valid BAR; MSE must be set before software can access
AHCI space.
• The Port Implemented bit (D31:F2, Offset ABAR+0Ch) for the corresponding port has to be set
to allow access to the AHCI port specific PxSSTS, PxSCRTL, and PxSERR registers.
8:0
SATA Initialization Field 1 (SIF1) — R/W. BIOS shall always program this register to the value
182h. All other values are reserved.
474
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet