82801FB Datasheet, PDF (345/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.3
PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
04–05h
0007h
No
Attribute:
Size:
Power Well:
R/W, RO
16-bit
Core
Bit
Description
15:10 Reserved
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8 SERR# Enable (SERR_EN) — R/W. The LPC bridge generates SERR# if this bit is set.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response Enable (PERE) — R/W.
6 _{0 = No action is taken when detecting a parity error.}
1 = Enables the ICH6 LPC bridge to respond to parity errors detected on backbone interface.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Memory Write and Invalidate Enable (MWIE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — RO. Bus Masters cannot be disabled.
1 Memory Space Enable (MSE) — RO. Memory space cannot be disabled on LPC.
0 I/O Space Enable (IOSE) — RO. I/O space cannot be disabled on LPC.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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