82801FB Datasheet, PDF (664/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.25
RIRBCTL—RIRB Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 5Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3 Reserved.
2
Response Overrun Interrupt Control — R/W. If this bit is set, the hardware will generate an
interrupt when the Response Overrun Interrupt Status bit (HDBAR + 5Dh: bit 2) is set.
Enable RIRB DMA Engine — R/W.
0 = DMA stop
1 ^{1 = DMA run}
After software writes a 0 to this bit, the hardware may not stop immediately. The hardware will
physically update the bit to 0 when the DMA engine is truly stopped. Software must read a 0 from
this bit to verify that the DMA engine is truly stopped.
Response Interrupt Control — R/W.
0 = Disable Interrupt
0 _{1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR when an}
empty Response slot is encountered on all SDI[x] inputs (whichever occurs first). The N counter
is reset when the interrupt is generated.
18.2.26
RIRBSTS—RIRB Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 5Dh
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
7:3 Reserved.
Response Overrun Interrupt Status — R/WC. Software sets this bit to 1 when the RIRB DMA
engine is not able to write the incoming responses to memory before additional incoming responses
overrun the internal FIFO. When the overrun occurs, the hardware will drop the responses which
2 _{overrun the buffer. An interrupt may be generated if the Response Overrun Interrupt Control bit is}
set. Note that this status bit is set even if an interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
1 Reserved.
Response Interrupt — R/WC. Hardware sets this bit to 1 when an interrupt has been generated
after N number of Responses are sent to the RIRB buffer OR when an empty Response slot is
0 ^{encountered on all SDI[x] inputs (whichever occurs first). Note that this status bit is set even if an}
interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
664
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet