82801FB Datasheet, PDF (327/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.3
PCICMD—PCI Command (PCI-PCI—D30:F0)
Offset Address: 04–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11 Reserved
10 Interrupt Disable (ID) — RO. Hardwired to 0. The PCI bridge has no interrupts to disable
9
Fast Back to Back Enable (FBE) — RO. Hardwired to 0, per the PCI Express* Base Specification,
Revision 1.0a.
SERR# Enable (SERR_EN) — R/W.
8
0 = Disable.
1 = Enable the ICH6 to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit
(offset 06h, bit 14) is set.
7
Wait Cycle Control (WCC) — RO. Hardwired to 0, per the PCI Express* Base Specification,
Revision 1.0a.
Parity Error Response (PER) — R/W.
6
0 = The ICH6 ignores parity errors on the PCI bridge.
1 = The ICH6 will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are detected on the
PCI bridge.
5
VGA Palette Snoop (VPS) — RO. Hardwired to 0, per the PCI Express* Base Specification,
Revision 1.0a.
4
Memory Write and Invalidate Enable (MWE) — RO. Hardwired to 0, per the PCI Express* Base
Specification, Revision 1.0a
3
Special Cycle Enable (SCE) — RO. Hardwired to 0, per the PCI Express* Base Specification,
Revision 1.0a and the PCI- to-PCI Bridge Specification.
Bus Master Enable (BME) — R/W.
2 _{0 = Disable}
1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.
Memory Space Enable (MSE) — R/W. Controls the response as a target for memory cycles
targeting PCI.
1
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI.
0 _{0 = Disable}
1 = Enable
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
327