82801FB Datasheet, PDF (395/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.1.2
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
Resume
Bit
Description
DRAM Initialization Bit — R/W. This bit does not effect hardware functionality in any way. BIOS is
expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after
completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence
7 _{was interrupted by a reset by reading this bit during the boot sequence.}
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
CPU PLL Lock Time (CPLT) — R/W. This field indicates the amount of time that the processor
needs to lock its PLLs. This is used wherever timing t270 (Chapter 22) applies.
00 = min 30.7 µs (Default)
01 = min 61.4 µs
6:5 ^{10 = min 122.8 µs}
11 = min 245.6 µs
It is the responsibility of the BIOS to program the correct value in this field prior to the first transition
to C3 or C4 states (or performing Intel SpeedStep^® technology transitions).
NOTE: The new DPSLP-TO-SLP bits (D31:F0:AAh, bits 1:0) act as an override to these bits.
NOTE: These bits are not cleared by any type of reset except RSMRST# or a CF9 write
System Reset Status (SRS) — R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
4 ^{1 = ICH6 sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit}
and clear it, if it is set.
NOTE: This bit is also reset by RSMRST# and CF9h resets.
CPU Thermal Trip Status (CTS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an
S0 or S1 state.
3 _NOTES:
1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the shutdown and reboot
associated with the CPUTHRMTRIP# event.
2. The CF9h reset in the description refers to CF9h type core well reset which includes SYS_RST#,
PWROK/VRMPWRGD low, SMBus hard reset, TCO Timeout. This type of reset will clear CTS
bit.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
395