82801FB Datasheet, PDF (756/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Electrical Characteristics
Table 22-22. Power Management Timings (Sheet 1 of 3)
Sym
Parameter
Min Max Units
Fig Notes
t230
VccSus active to SLP_S5#, SLP_S4#, SLP_S3#,
SUS_STAT#, PLTRST# and PCIRST# active
t231 _{RSMRST# inactive to SUSCLK running, SLP_S5#}
t232 ^inactive
t233 SLPS5# inactive to SLP_S4# inactive
t234 SLPS4# inactive to SLP_S3# inactive
Processor I/F signals latched prior to STPCLK#
t250 ^active
(Mobile Only)
Bus Master Idle to CPU_SLP# active
t251
(Mobile Only)
t252
CPUSLP# active to DPSLP# active
(Mobile Only)
t253
DPSLP# active to STP_CPU# active
(Mobile Only)
STP_CPU# active to processor clock stopped
t254
(Mobile Only)
STP_CPU# active to DPRSTP#, DPRSLPVR active
t255
(Mobile Only)
Break Event to DPRSTP#, DPRSLPVR inactive
t265 _{(C4 Exit)}
(Mobile Only)
DPRSLPVR, DPRSTP# inactive to STP_CPU#
t266 inactive and CPU Vcc ramped
(Mobile Only)
Break Event to STP_CPU# inactive
t267 (C3 Exit)
(Mobile Only)
STP_CPU# inactive to processor clock running
t268
(Mobile Only)
STP_CPU# inactive to DPSLP# inactive
t269
(Mobile Only)
DPSLP# inactive to CPU_SLP# inactive
t270
(Mobile Only)
t271
S1 Wake Event to CPUSLP# inactive
(Desktop Only)
CPUSLP# inactive to STPCLK# inactive
t272
(Mobile Only)
Break Event to STPCLK# inactive
t273 (C2 Exit)
(Mobile Only)
–
50
ns
– 110
ms
See Note Below
1
2 RTCCLK
0
–
2.88 – PCICLK
16
– PCICLK
1
1 PCICLK
0
– PCICLK
0
–
1.5 1.8
µs
Programable.
See
D31:F0:AA,
µs
bits 3:2
6
Note
14
PCICLK
0
3 PCICLK
1
1 PCICLK
Program-
mable. See
D31:F0:AAh,
µs
bits 1:0
1
25 PCICLK
0
–
µs
0
–
ns
22-20
22-21
22-20
22-21
22-20
22-21
22-20
22-21
22-27
22-28
22-29
22-28
22-29
22-28
22-29
22-28
22-29
22-28
22-29
22-29
22-29
22-29
22-28
22-28
22-29
22-28
22-29
22-28
22-29
22-22
22-28
22-29
22-27
1
2
3
4
5, 6
5
5
5, 7
8
5, 9,10
5, 7
5,11
11
5
756
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet