82801FB Datasheet, PDF (107/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Error Handling
Data Parity Errors: The LAN controller checks for data parity errors while it is the target of the
transaction. If an error was detected, the LAN controller always sets the Detected Parity Error bit in
the PCI Configuration Status register, bit 15. The LAN controller also asserts PERR#, if the Parity
Error Response bit is set (PCI Configuration Command register, bit 6). The LAN controller does
not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the
option of recovery.
Target-Disconnect: The LAN controller prematurely terminate a cycle in the following cases:
• After accesses to its CSR
• After accesses to the configuration space
System Error: The LAN controller reports parity error during the address phase using the SERR#
pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error
Response bit are not set, the LAN controller only sets the Detected Parity Error bit (PCI
Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set,
the LAN controller sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as
well as the Detected Parity Error bit and asserts SERR# for one clock.
The LAN controller, when detecting system error, claims the cycle if it was the target of the
transaction and continues the transaction as if the address was correct.
Note: The LAN controller reports a system error for any error during an address phase, whether or not it
is involved in the current transaction.
5.3.1.2
CLKRUN# Signal (Mobile Only)
The ICH6 receives a free-running 33 MHz clock. It does not stop based on the CLKRUN# signal
and protocol. When the LAN controller runs cycles on the PCI bus, the ICH6 makes sure that the
STP_PCI# signal is high indicating that the PCI clock will be running. This is to make sure that any
PCI tracker does not get confused by transactions on the PCI bus with its PCI clock stopped.
5.3.1.3
PCI Power Management
Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.3,
is provided in the ICH6 integrated LAN controller. The LAN controller supports a large set of
wake-up packets and the capability to wake the system from a low power state on a link status
change. The LAN controller enables the host system to be in a sleep state and remain virtually
connected to the network.
After a power management event or link status change is detected, the LAN controller wakes the
host system. The sections below describe these events, the LAN controller power states, and
estimated power consumption at each power state.
The LAN controller contains power management registers for PCI, and implements four power
states, D0 through D3, which vary from maximum power consumption at D0 to the minimum
power consumption at D3. PCI transactions are only allowed in the D0 state, except for host
accesses to the LAN controller’s PCI configuration registers. The D1 and D2 power management
states enable intermediate power savings while providing the system wake-up capabilities. In the
D3_COLD state, the LAN controller can provide wake-up capabilities. Wake-up indications from the
LAN controller are provided by the Power Management Event (PME#) signal.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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