82801FB Datasheet, PDF (5/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
5.5.1 LPC Interface .......................................................................................................116
5.5.1.1 LPC Cycle Types .................................................................................117
5.5.1.2 Start Field Definition.............................................................................117
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ...........................................118
5.5.1.4 SIZE .....................................................................................................118
5.5.1.5 SYNC ...................................................................................................119
5.5.1.6 SYNC Time-Out ...................................................................................119
5.5.1.7 SYNC Error Indication..........................................................................119
5.5.1.8 LFRAME# Usage .................................................................................119
5.5.1.9 I/O Cycles ............................................................................................120
5.5.1.10 Bus Master Cycles ...............................................................................120
5.5.1.11 LPC Power Management .....................................................................120
5.5.1.12 Configuration and Intel^® ICH6 Implications..........................................120
5.6 DMA Operation (D31:F0) ..................................................................................................121
5.6.1 Channel Priority ...................................................................................................122
5.6.1.1 Fixed Priority ........................................................................................122
5.6.1.2 Rotating Priority ...................................................................................122
5.6.2 Address Compatibility Mode ................................................................................122
5.6.3 Summary of DMA Transfer Sizes ........................................................................123
5.6.3.1 Address Shifting When Programmed for 16-Bit
I/O Count by Words .............................................................................123
5.6.4 Autoinitialize.........................................................................................................123
5.6.5 Software Commands ...........................................................................................124
5.7 LPC DMA..........................................................................................................................124
5.7.1 Asserting DMA Requests.....................................................................................124
5.7.2 Abandoning DMA Requests ................................................................................125
5.7.3 General Flow of DMA Transfers ..........................................................................125
5.7.4 Terminal Count ....................................................................................................126
5.7.5 Verify Mode..........................................................................................................126
5.7.6 DMA Request De-assertion .................................................................................126
5.7.7 SYNC Field / LDRQ# Rules .................................................................................127
5.8 8254 Timers (D31:F0).......................................................................................................128
5.8.1 Timer Programming .............................................................................................128
5.8.2 Reading from the Interval Timer ..........................................................................129
5.8.2.1 Simple Read ........................................................................................130
5.8.2.2 Counter Latch Command .....................................................................130
5.8.2.3 Read Back Command ..........................................................................130
5.9 8259 Interrupt Controllers (PIC) (D31:F0) ........................................................................131
5.9.1 Interrupt Handling ................................................................................................132
5.9.1.1 Generating Interrupts ...........................................................................132
5.9.1.2 Acknowledging Interrupts.....................................................................132
5.9.1.3 Hardware/Software Interrupt Sequence...............................................133
5.9.2 Initialization Command Words (ICWx) .................................................................133
5.9.2.1 ICW1 ....................................................................................................133
5.9.2.2 ICW2 ....................................................................................................134
5.9.2.3 ICW3 ....................................................................................................134
5.9.2.4 ICW4 ....................................................................................................134
5.9.3 Operation Command Words (OCW) ....................................................................134
5.9.4 Modes of Operation .............................................................................................134
5.9.4.1 Fully Nested Mode ...............................................................................134
5.9.4.2 Special Fully-Nested Mode ..................................................................135
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices) ..............................135
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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