82801FB Datasheet, PDF (690/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.25
DCTL—Device Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 48–49h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15
14:12
11
10
9
8
7:5
4
3
2
1
0
Reserved
Max Read Request Size (MRRS) — RO. Hardwired to 0.
Enable No Snoop (ENS) — RO. Not supported. The root port will never issue non-snoop requests.
Aux Power PM Enable (APME) — R/W. The OS will set this bit to 1 if the device connected has
detected aux power. It has no effect on the root port otherwise.
Phantom Functions Enable (PFE) — RO. Not supported.
Extended Tag Field Enable (ETFE) — RO. Not supported.
Max Payload Size (MPS) — R/W. The root port only supports 128-B payloads, regardless of the
programming of this field.
Enable Relaxed Ordering (ERO) — RO. Not supported.
Unsupported Request Reporting Enable (URE) — R/W.
0 = The root port will ignore unsupported request errors.
1 = The root port will generate errors when detecting an unsupported request.
Fatal Error Reporting Enable (FEE) — R/W.
0 = The root port will ignore fatal errors.
1 = The root port will generate errors when detecting a fatal error.
Non-Fatal Error Reporting Enable (NFE) — R/W.
0 = The root port will ignore non-fatal errors.
1 = The root port will generate errors when detecting a non-fatal error.
Correctable Error Reporting Enable (CEE) — R/W.
0 = The root port will ignore correctable errors.
1 = The root port will generate errors when detecting a correctable error.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet