82801FB Datasheet, PDF (348/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.9
PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Master Latency Count (MLC) — Reserved.
2:0 Reserved.
10.1.10
HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh
Default Value: 80h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
6:0 Header Type — RO. This 7-bit field identifies the header layout of the configuration space.
10.1.11
SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2C–2Fh
Default Value: 00000000h
Attribute:
Size:
R/WO
32 bits
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only
once after PLTRST# de-assertion.
Bit
Description
31:16
15:0
Subsystem ID (SSID) — R/WO. This field is written by BIOS. No hardware action taken on this
value.
Subsystem Vendor ID (SSVID) — R/WO. This field is written by BIOS. No hardware action taken
on this value.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet