82801FB Datasheet, PDF (328/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06–07h
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 ^{0 = Parity error Not detected.}
1 = Indicates that the ICH6 detected a parity error on the internal backbone. This bit gets set even if
the Parity Error Response bit (D30:F0:04 bit 6) is not set.
Signaled System Error (SSE) — R/WC. Several internal and external sources of the bridge can
cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge
captures generic data parity errors (errors it finds on the backbone) as well as errors returned on
backbone cycles where the bridge was the master. If either of these two conditions is met, and the
primary side of the bridge is enabled for parity error response, SERR# will be captured as shown
below.
As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge captures
generic data parity errors (errors it finds on PCI) as well as errors returned on PCI cycles where the
bridge was the master. If either of these two conditions is met, and the secondary side of the bridge
is enabled for parity error response, SERR# will be captured as shown below.
14 _{The final class of errors is system bus errors. There are three status bits associated with system bus}
errors, each with a corresponding enable. The diagram capturing this is shown below.
After checking for the three above classes of errors, an SERR# is generated, and PSTS.SSE logs
the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown below.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet