82801FB Datasheet, PDF (374/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.4.3
10.4.4
ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Master Controller – 21h
Slave Controller – A1h
All bits undefined
Attribute:
Size:
WO
8 bit /controller
ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt
vector address. The value programmed for bits[7:3] is used by the processor to define the base
address in the interrupt vector table for the interrupt routines associated with each IRQ on the
controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave
controller.
Bit
Description
7:3
Interrupt Vector Base Address — WO. Bits [7:3] define the base address in the interrupt vector
table for the interrupt routines associated with each interrupt request level input.
Interrupt Request Level — WO. When writing ICW2, these bits should all be 0. During an interrupt
acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be
serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during
the second INTA# cycle. The code is a three bit binary code:
Code
Master Interrupt
Slave Interrupt
000b
IRQ0
IRQ8
2:0
001b
IRQ1
IRQ9
010b
IRQ2
IRQ10
011b
IRQ3
IRQ11
100b
IRQ4
IRQ12
101b
IRQ5
IRQ13
110b
IRQ6
IRQ14
111b
IRQ7
IRQ15
ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0)
Offset Address: 21h
Default Value: All bits undefined
Attribute:
Size:
WO
8 bits
Bit
Description
7:3 0 = These bits must be programmed to 0.
Cascaded Interrupt Controller IRQ Connection — WO. This bit indicates that the slave controller
is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave controller’s priority
2
resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master
controller’s priority solver. If it wins, the INTR signal is asserted to the processor, and the returning
interrupt acknowledge returns the interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
1:0 0 = These bits must be programmed to 0.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet