82801FB Datasheet, PDF (425/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
Bit
Description
BIOSWR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH6 sets this bit and generates and SMI# to indicate an illegal attempt to write to the BIOS.
This occurs when either:
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a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
NOTE: On write cycles attempted to the 4 MB lower alias to the BIOS space, the BIOSWR_STS
will not be set.
NEWCENTURY_STS — R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from 99 to 00.
Setting this bit will cause an SMI# (but not a wake event).
NOTE: The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or when
RTC power has not been maintained). Software can determine if RTC power has not been
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maintained by checking the RTC_PWR_STS bit (D31:F0:A4h, bit 2), or by other means
(such as a checksum on RTC RAM). If RTC power is determined to have not been
maintained, BIOS should set the time to a legal value and then clear the
NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a 1
is written to the bit to clear it. After writing a 1 to this bit, software should not exit the SMI
handler until verifying that the bit has actually been cleared. This will ensure that the SMI is
not re-entered.
6:4 Reserved
TIMEOUT — R/WC.
3 _{0 = Software clears this bit by writing a 1 to it.}
1 = Set by ICH6 to indicate that the SMI was caused by the TCO timer reaching 0.
TCO_INT_STS — R/WC.
2 _{0 = Software clears this bit by writing a 1 to it.}
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register (TCOBASE + 03h).
SW_TCO_SMI — R/WC.
1 _{0 = Software clears this bit by writing a 1 to it.}
1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h).
NMI2SMI_STS — RO.
0 ^{0 = Cleared by clearing the associated NMI status bit.}
1 = Set by the ICH6 when an SMI# occurs because an event occurred that would otherwise have
caused an NMI (because NMI2SMI_EN is set).
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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