82801FB Datasheet, PDF (524/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

UHCI Controllers Registers
13.2.7 PORTSC[0,1]—Port Status and Control Register
I/O Offset:
Default Value:
Port 0/2/4/6: Base + (10–11h)
Port 1/3/5/7: Base + (12–13h)
0080h
Attribute: R/WC, RO,
R/W (Word writes only)
Size: 16 bits
Note: For Function 0, this applies to ICH6 USB ports 0 and 1; for Function 1, this applies to ICH6 USB
ports 2 and 3; for Function 2, this applies to ICH6 USB ports 4 and 5; and for Function 3, this
applies to ICH6 USB ports 6 and 7.
After a power-up reset, global reset, or host controller reset, the initial conditions of a port are: no
device connected, Port disabled, and the bus line status is 00 (single-ended 0).
Port Reset and Enable Sequence
When software wishes to reset a USB device it will assert the Port Reset bit in the Port Status and
Control register. The minimum reset signaling time is 10 mS and is enforced by software. To
complete the reset sequence, software clears the port reset bit. The Intel UHCI controller must re-
detect the port connect after reset signaling is complete before the controller will allow the port
enable bit to de set by software. This time is approximately 5.3 uS. Software has several possible
options to meet the timing requirement and a partial list is inumerated below:
• Iterate a short wait, setting the port enable bit and reading it back to see if the enable bit is set.
• Poll the connect status bit and wait for the hardware to recognize the connect prior to enabling
the port.
• Wait longer than the hardware detect time after clearing the port reset and prior to enabling the
port.
Bit
Description
15:13
12
Reserved — RO.
Suspend — R/W. This bit should not be written to a 1 if global suspend is active (bit 3=1 in the
USBCMD register). Bit 2 and bit 12 of this register define the hub states as follows:
Bits [12,2]
Hub State
X,0
Disable
0, 1
Enable
1, 1
Suspend
When in suspend state, downstream propagation of data is blocked on this port, except for
single-ended 0 resets (global reset and port reset). The blocking occurs at the end of the current
transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the
port is sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction currently in
progress on the USB.
1 = Port in suspend state.
0 = Port not in suspend state.
NOTE: Normally, if a transaction is in progress when this bit is set, the port will be suspended when
the current transaction completes. However, in the case of a specific error condition (out
transaction with babble), the ICH6 may issue a start-of-frame, and then suspend the port.
Overcurrent Indicator — R/WC. Set by hardware.
11 _{0 = Software clears this bit by writing a 1 to it.}
1 = Overcurrent pin has gone from inactive to active on this port.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet