82801FB Datasheet, PDF (470/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.25 IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F2)
Address Offset: 54h–57h
Default Value: 00000000h
Attribute: R/W
Size:
32 bits
Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when
the PCI functions are combined. These bits have no effect on SATA operation, unless otherwise
noted.
Bit
Description
31:24
23:20
19:18
17:16
15
14
13
12
11:8
7:4
Reserved
Scratchpad (SP2). Intel^® ICH6 does not perform any actions on these bits.
SEC_SIG_MODE — R/W. These bits are used to control mode of the Secondary IDE signal pins for
swap bay support.
If the SRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states of bits 19:18
will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
PRIM_SIG_MODE — R/W. These bits are used to control mode of the Primary IDE signal pins for
mobile swap bay support.
If the PRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states of bits 17:16
will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
Fast Secondary Drive 1 Base Clock (FAST_SCB1) — R/W. This bit is used in conjunction with the
SCT1 bits (D31:F2:4Ah, bits 13:12) to enable/disable Ultra ATA/100 timings for the Secondary Slave
drive.
0 = Disable Ultra ATA/100 timing for the Secondary Slave drive.
1 = Enable Ultra ATA/100 timing for the Secondary Slave drive (overrides bit 3 in this register).
Fast Secondary Drive 0 Base Clock (FAST_SCB0) — R/W. This bit is used in conjunction with the
SCT0 bits (D31:F2:4Ah, bits 9:8) to enable/disable Ultra ATA/100 timings for the Secondary Master
drive.
0 = Disable Ultra ATA/100 timing for the Secondary Master drive.
1 = Enable Ultra ATA/100 timing for the Secondary Master drive (overrides bit 2 in this register).
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in conjunction with the
PCT1 bits (D31:F2:4Ah, bits 5:4) to enable/disable Ultra ATA/100 timings for the Primary Slave
drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in conjunction with the
PCT0 bits (D31:F2:4Ah, bits 1:0) to enable/disable Ultra ATA/100 timings for the Primary Master
drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).
Reserved
Scratchpad (SP1). ICH6 does not perform any action on these bits.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet