82801FB Datasheet, PDF (471/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
Bit
Description
Secondary Drive 1 Base Clock (SCB1) — R/W.
3 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
Secondary Drive 0 Base Clock (SCBO) — R/W.
2 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 1 Base Clock (PCB1) — R/W.
1 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 0 Base Clock (PCB0) — R/W.
0 _{0 = 33 MHz base clock for Ultra ATA timings.}
1 = 66 MHz base clock for Ultra ATA timings
12.1.26 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset: 70–71h
Default Value: 0001h
Attribute:
Size:
RO
16 bits
Bits
Description
15:8 Next Capability (NEXT) — RO. Indicates that this is the last item in the list.
7:0 Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
12.1.27
f
PC—PCI Power Management Capabilities Register
(SATA–D31:F2)
Address Offset: 72–73h
Default Value: 4002h
Attribute:
Size:
RO
16 bits
Bits
Description
15:11
10
9
8:6
5
4
3
2:0
PME Support (PME_SUP) — RO. This field indicates PME# can be generated from the D3_HOT state
in the SATA host controller.
D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR) — RO. PME# from D3_COLD state is not supported, therefore this field
is 000b.
Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-specific
initialization is required.
Reserved
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to generate
PME#.
Version (VER) — RO. Hardwired to 010 to indicates support for Revision 1.1 of the PCI Power
Management Specification.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
471