82801FB Datasheet, PDF (424/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.9.2
10.9.3
10.9.4
TCO_DAT_IN—TCO Data In Register
I/O Address:
Default Value:
Lockable:
TCOBASE +02h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
TCO Data In Value — R/W. This data register field is used for passing commands from the OS to
7:0 the SMI handler. Writes to this register will cause an SMI and set the SW_TCO_SMI bit in the
TCO1_STS register (D31:F0:04h).
TCO_DAT_OUT—TCO Data Out Register
I/O Address:
Default Value:
Lockable:
TCOBASE +03h
00h
No
Attribute:
Size:
Power Well:
R/W
8-bit
Core
Bit
Description
TCO Data Out Value — R/W. This data register field is used for passing commands from the SMI
7:0 handler to the OS. Writes to this register will set the TCO_INT_STS bit in the TCO_STS register. It
will also cause an interrupt, as selected by the TCO_INT_SEL bits.
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
TCOBASE +04h
0000h
No
Attribute:
Size:
Power Well:
R/WC, RO
16-bit
Core
(Except bit 7, in RTC)
Bit
Description
15:13
12
11
10
9
Reserved
DMISERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH6 received a DMI special cycle message via DMI indicating that it wants to cause an
SERR#. The software must read the (G)MCH to determine the reason for the SERR#.
Reserved
DMISMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH6 received a DMI special cycle message via DMI indicating that it wants to cause an SMI.
The software must read the (G)MCH to determine the reason for the SMI.
DMISCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH6 received a DMI special cycle message via DMI indicating that it wants to cause an SCI.
The software must read the (G)MCH to determine the reason for the SCI.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet