82801FB Datasheet, PDF (100/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.1.4
PCIRST#
The PCIRST# pin is generated under two conditions:
• PLTRST# active
• BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1
The PCIRST# pin is in the resume well. PCIRST# should be tied to PCI bus agents, but not other
agents in the system.
5.1.5 Peer Cycles
The following peer cycles are supported: PCI Express to PCI Express Graphics (writes only), PCI
to PCI Express Graphics (writes only) and PCI to PCI.
Note: The ICH6’s AC ’97, IDE and USB controllers cannot perform peer-to-peer traffic.
5.1.6
PCI-to-PCI Bridge Model
From a software perspective, the ICH6 contains a PCI-to-PCI bridge. This bridge connects DMI to
the PCI bus. By using the PCI-to-PCI bridge software model, the ICH6 can have its decode ranges
programmed by existing plug-and-play software such that PCI ranges do not conflict with graphics
aperture ranges in the Host controller.
5.1.7
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH6 asserts one address
signal as an IDSEL. When accessing device 0, the ICH6 asserts AD16. When accessing Device 1,
the ICH6 asserts AD17. This mapping continues all the way up to device 15 where the ICH6
asserts AD31. Note that the ICH6’s internal functions (AC ’97, Intel High Definition Audio, IDE,
USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the
external PCI bus. The integrated LAN controller is Device 8 on the ICH6’s PCI bus, and hence it
uses AD[24] for IDSEL.
5.1.8 Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to
eight functions with each function containing up to 256, 8-bit configuration registers. The PCI
Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space:
Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the
processor. Configuration space is supported by a mapping mechanism implemented within the
ICH6. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access
configuration space, Mechanism 1 and Mechanism 2. The ICH6 only supports Mechanism 1.
Warning: Configuration writes to internal devices, when the devices are disabled, are illegal and may cause
undefined results.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet