82801FB Datasheet, PDF (569/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2 SMBus I/O Registers
Table 15-2. SMBus I/O Register Address Map
SMB_BASE
+ Offset
Mnemonic
Register Name
00h
HST_STS
Host Status
02h
03h
04h
05h
06h
07h
08h
09h
0A–0Bh
0Ch
0Dh
0Eh
0Fh
HST_CNT
HST_CMD
XMIT_SLVA
HST_D0
HST_D1
HOST_BLOCK_DB
PEC
RCV_SLVA
SLV_DATA
AUX_STS
AUX_CTL
SMLINK_PIN_CTL
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Packet Error Check
Receive Slave Address
Receive Slave Data
Auxiliary Status
Auxiliary Control
SMLink Pin Control (TCO
Compatible Mode)
SMBus_PIN_CTL SMBus Pin Control
10h
SLV_STS
Slave Status
11h
SLV_CMD
Slave Command
14h
NOTIFY_DADDR Notify Device Address
16h
NOTIFY_DLOW
Notify Data Low Byte
17h
NOTIFY_DHIGH Notify Data High Byte
Default
Type
00h
00h
00h
00h
00h
00h
00h
00h
44h
0000h
00h
00h
See register
description
See register
description
00h
00h
00h
00h
00h
R/WC, RO,
R/WC (special)
R/W, WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
R/WC, RO
R/W
R/W, RO
R/W, RO
R/WC
R/W
RO
RO
RO
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
569