82801FB Datasheet, PDF (325/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9 PCI-to-PCI Bridge Registers
(D30:F0)
The ICH6 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the
buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is
handled by this PCI device.
9.1
PCI Configuration Registers (D30:F0)
Note: Address locations that are not shown should be treated as Reserved (see Section 6.2 for details).
.
Table 9-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 1 of 2)
Offset
00–01h
Mnemonic
VID
Register Name
Vendor Identification
02–03h DID
Device Identification
04–05h
06–07h
PCICMD
PSTS
PCI Command
PCI Status
08h
RID
Revision Identification
09-0Bh
0Dh
0Eh
18-1Ah
1Bh
1C-1Dh
1E–1Fh
20–23h
24–27h
28–2Bh
2C–2Fh
34h
3C-3Dh
3E–3Fh
40–41h
CC
PMLT
HEADTYP
BNUM
SMLT
IOBASE_LIMIT
SECSTS
MEMBASE_LIMIT
PREF_MEM_BASE
_LIMIT
PMBU32
PMLU32
CAPP
INTR
BCTRL
SPDH
Class Code
Primary Master Latency Timer
Header Type
Bus Number
Secondary Master Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
Prefetchable Memory Base and Limit
Prefetchable Memory Upper 32 Bits
Prefetchable Memory Limit Upper 32 Bits
Capability List Pointer
Interrupt Information
Bridge Control
Secondary PCI Device Hiding
Default
8086h
244Eh
(Desktop)
2448h
(ICH6-M)
0000h
0010h
See
register
description.
060401h
00h
81h
000000h
00h
0000h
0280h
00000000h
Type
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/WC, RO
R/W, RO
00010001h R/W, RO
00000000h
00000000h
50h
0000h
0000h
00h
R/W
R/W
RO
R/W, RO
R/WC, RO
R/W, RO
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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