82801FB Datasheet, PDF (693/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.28
LCTL—Link Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 50–51h
Default Value: 0000h
Attribute:
Size:
R/W, WO, RO
16 bits
Bit
Description
15:8 Reserved
Extended Synch (ES) — R/W.
7 ^{0 = Extended synch disabled.}
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from L1 prior to
entering L0.
Common Clock Configuration (CCC) — R/W.
6 _{0 = The ICH6 and device are not using a common reference clock.}
1 = The ICH6 and device are operating with a distributed common reference clock.
Retrain Link (RL) — WO.
0 = This bit always returns 0 when read.
5 _{1 = The root port will train its downstream link.}
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3:52, bit 11) to check the status of training.
Link Disable (LD) — R/W.
4 _{0 = Link enabled.}
1 = The root port will disable the link.
3
Read Completion Boundary Control (RCBC) — RO. This bit indicates the read completion
boundary is 64 bytes.
2 Reserved
Active State Link PM Control (APMC) — R/W. This field indicates whether the root port should
enter L0s or L1 or both.
Bits
Definition
1:0
00b
Disabled
01b
L0s Entry is Enabled
10b
L1 Entry is Enabled
11b
L0s and L1 Entry Enabled
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
693