82801FB Datasheet, PDF (663/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.22
RIRBUBASE—RIRB Upper Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 54h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
RIRB Upper Base Address — R/W. Upper 32 bits of the address of the Response Input Ring
31:0 Buffer. This register field must not be written when the DMA engine is running or the DMA transfer
may be corrupted.
18.2.23
RIRBWP—RIRB Write Pointer Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 58h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB Write Pointer to
0. The RIRB DMA engine must be stopped prior to resetting the Write Pointer or else DMA transfer
15 _{may be corrupted.}
This bit is always read as 0.
14:8 Reserved.
RIRB Write Pointer (RIRBWP) — RO. Indicates the last valid RIRB entry written by the DMA
controller. Software reads this field to determine how many responses it can read from the RIRB.
7:0 The value read indicates the RIRB Write Pointer offset in 2 DWord RIRB entry units (since each
RIRB entry is 2 DWords long). Supports up to 256 RIRB entries (256 x 8 B = 2 KB). This register
field may be written when the DMA engine is running.
18.2.24
RINTCNT—Response Interrupt Count Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 5Ah
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:8 Reserved.
N Response Interrupt Count — R/W.
0000 0001b = 1 response sent to RIRB
...........
1111 1111b = 255 responses sent to RIRB
31:0 ^{0000 0000b = 256 responses sent to RIRB}
The DMA engine should be stopped when changing this field or else an interrupt may be lost.
Note that each response occupies 2 DWords in the RIRB.
This is compared to the total number of responses that have been returned, as opposed to the
number of frames in which there were responses. If more than one codecs responds in one frame,
then the count is increased by the number of responses received in the frame.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
663