82801FB Datasheet, PDF (218/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Block Write–Block Read Process Call
The block write-block read process call is a two-part message. The call begins with a slave address
and a write condition. After the command code the host issues a write byte count (M) that describes
how many more bytes will be written in the first part of the message. If a master has 6 bytes to
send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The
write byte count (M) cannot be 0.
The second part of the message is a block of read data beginning with a repeated start condition
followed by the slave address and a Read bit. The next byte is the read byte count (N), which may
differ from the write byte count (M). The read byte count (N) cannot be 0.
The combined data payload must not exceed 32 bytes. The byte length restrictions of this process
call are summarized as follows:
• M ≥ 1 byte
• N ≥ 1 byte
• M + N ≤ 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total message
beginning with the first slave address and using the normal PEC computational rules. It is highly
recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software
must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to
reading the block data register.
Note that there is no STOP condition before the repeated START condition, and that a NACK
signifies the end of the read transfer.
Note: E32B bit in the Auxiliary Control register must be set when using this protocol.
See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format
of the protocol.
5.21.2 Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low
to signal a start condition. The ICH6 continuously monitors the SMBDATA line. When the ICH6 is
attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA
low, then some other master is driving the bus and the ICH6 will stop transferring data.
If the ICH6 sees that it has lost arbitration, the condition is called a collision. The ICH6 will set the
BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The
processor is responsible for restarting the transaction.
When the ICH6 is a SMBus master, it drives the clock. When the ICH6 is sending address or
command as an SMBus master, or data bytes as a master on writes, it drives data relative to the
clock it is also driving. It will not start toggling the clock until the start or stop condition meets
proper setup and hold time. The ICH6 will also guarantee minimum time between SMBus
transactions as a master.
Note: The ICH6 supports the same arbitration protocol for both the SMBus and the System Management
(SMLINK) interfaces.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet