82801FB Datasheet, PDF (381/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.5.3
DAT—Data Register (LPC I/F—D31:F0)
Memory Address FEC0_0010h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This is a 32-bit register specifying the data to be read or written to the register pointed to by the
Index register. This register can only be accessed in DWord quantities.
Bit
Description
7:0
APIC Data — R/W. This is a 32-bit register for the data to be read or written to the APIC indirect
register (Figure 10-5) pointed to by the Index register (Memory Address FEC0_0000h).
10.5.4 EOIR—EOI Register (LPC I/F—D31:F0)
Memory Address FEC0_0040h
Default Value: N/A
Attribute:
Size:
WO
32 bits
The EOI register is present to provide a mechanism to maintain the level triggered semantics for
level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this
register, and compare it with the vector field for each entry in the I/O Redirection Table. When a
match is found, the Remote_IRR bit (Index Offset 10h, bit 14) for that I/O Redirection Entry will
be cleared.
Note:
If multiple I/O Redirection entries, for any reason, assign the same vector for more than one
interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt which
was prematurely reset will not be lost because if its input remained active when the Remote_IRR
bit is cleared, the interrupt will be reissued and serviced at a later time. Note: Only bits 7:0 are
actually used. Bits 31:8 are ignored by the ICH6.
Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8.
Bit
Description
31:8
Reserved. To provide for future expansion, the processor should always write a value of 0 to
Bits 31:8.
Redirection Entry Clear — WO. When a write is issued to this register, the I/O APIC will check this
7:0 field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match
is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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