82801FB Datasheet, PDF (61/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-7. Serial ATA Interface Signals (Sheet 2 of 2)
Name
SATA[0]GP /
GPI[26]
Type
I
Description
Serial ATA 0 General Purpose: This is an input pin that can be configured as
an interlock switch corresponding to SATA Port 0. When used as an interlock
switch status indication, this signal should be drive to 0 to indicate that the
switch is closed and to 1 to indicate that the switch is open.
If interlock switches are not required, this pin can be configured as GPI[26].
SATA[1]GP
(Desktop Only) /
GPI[29]
SATA[2]GP /
GPI[30]
SATA[3]GP
(Desktop Only) /
GPI[31]
SATALED#
I
I
I
OC O
NOTE: All SATAxGP pins must be configured with the same function: as either
SATAxGP pins or GPI pins.
Serial ATA 1 General Purpose: Same function as SATA[0]GP, except for SATA
Port 1.
If interlock switches are not required, this pin can be configured as GPI[29].
Serial ATA 2 General Purpose: Same function as SATA[0]GP, except for SATA
Port 2.
If interlock switches are not required, this pin can be configured as GPI[30].
Serial ATA 3 General Purpose: Same function as SATA[0]GP, except for SATA
Port 3.
If interlock switches are not required, this pin can be configured as GPI[31].
Serial ATA LED: This is an open-collector output pin driven during SATA
command activity. It is to be connected to external circuitry that can provide the
current to drive a platform LED. When active, the LED is on. When tri-stated,
the LED is off. An external pull-up resistor to Vcc3_3 is required.
NOTE: An internal pull-up is enabled only during PLTRST# assertion.
2.8
IDE Interface
Table 2-8. IDE Interface Signals (Sheet 1 of 2)
Name
DCS1#
DCS3#
DA[2:0]
DD[15:0]
DDREQ
DDACK#
Type
Description
O
IDE Device Chip Selects for 100 Range: For ATA command register block. This
output signal is connected to the corresponding signal on the IDE connector.
O
IDE Device Chip Select for 300 Range: For ATA control register block. This output
signal is connected to the corresponding signal on the IDE connector.
IDE Device Address: These output signals are connected to the corresponding
O signals on the IDE connector. They are used to indicate which byte in either the
ATA command block or control block is being addressed.
I/O
IDE Device Data: These signals directly drive the corresponding signals on the IDE
connector. There is a weak internal pull-down resistor on DD7.
IDE Device DMA Request: This input signal is directly driven from the DRQ signal
on the IDE connector. It is asserted by the IDE device to request a data transfer,
I and used in conjunction with the PCI bus master IDE function and are not
associated with any AT compatible DMA channel. There is a weak internal pull-
down resistor on this signal.
IDE Device DMA Acknowledge: This signal directly drives the DAK# signal on the
IDE connector. DDACK# is asserted by the Intel^® ICH6 to indicate to IDE DMA
O slave devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus master
IDE function and are not associated with any AT-compatible DMA channel.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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