82801FB Datasheet, PDF (551/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
Bit
Description
Frame List Rollover — R/WC.
0 = No Frame List Index rollover from its maximum value to 0.
3 _{1 = The Host controller sets this bit to a 1 when the Frame List Index (see Section) rolls over from its}
maximum value to 0. Since the ICH6 only supports the 1024-entry Frame List Size, the Frame
List Index rolls over every time FRNUM13 toggles.
Port Change Detect — R/WC. This bit is allowed to be maintained in the Auxiliary power well.
Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is
loaded with the OR of all of the PORTSC change bits (including: Force port resume, overcurrent
change, enable/disable change and connect status change). Regardless of the implementation,
when this bit is readable (i.e., in the D0 state), it must provide a valid view of the Port Status registers.
2
0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0 to 1 as a
result of a J-K transition detected on a suspended port.
1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is set to 0 has a
change bit transition from a 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a result of
a J-K transition detected on a suspended port.
USB Error Interrupt (USBERRINT) — R/WC.
0 = No error condition.
1 ^{1 = The Host controller sets this bit to 1 when completion of a USB transaction results in an error}
condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had
its IOC bit set, both this bit and Bit 0 are set. See the EHCI specification for a list of the USB
errors that will result in this interrupt being asserted.
USB Interrupt (USBINT) — R/WC.
0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set. No short
packet is detected.
0 _{1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion of a USB}
transaction whose Transfer Descriptor had its IOC bit set.
The Host controller also sets this bit to 1 when a short packet is detected (actual number of
bytes received was less than the expected number of bytes).
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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