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82801FB Datasheet, PDF (299/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family
LAN Controller Registers (B1:D8:F0)
Table 8-5. Self-Test Results Format
Bit
Description
31:13
12
11:6
5
4
3
2
1:0
Reserved
General Self-Test Result (SELF_TST) — R/W (special).
0 = Pass
1 = Fail
Reserved
Diagnose Result (DIAG_RSLT) — R/W (special). This bit provides the result of an internal
diagnostic test of the Serial Subsystem.
0 = Pass
1 = Fail
Reserved
Register Result (REG_RSLT) — R/W (special). This bit provides the result of a test of the internal
Parallel Subsystem registers.
0 = Pass
1 = Fail
ROM Content Result (ROM_RSLT) — R/W (special). This bit provides the result of a test of the
internal microcode ROM.
0 = Pass
1 = Fail
Reserved
8.2.5
EEPROM_CNTL—EEPROM Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO, R/W, WO
8 bits
The EEPROM Control Register is a 16-bit field that enables a read from and a write to the external
EEPROM.
Bit
Description
7:4 Reserved
EEPROM Serial Data Out (EEDO) — RO. Note that this bit represents “Data Out” from the
3 perspective of the EEPROM device. This bit contains the value read from the EEPROM when
performing read operations.
EEPROM Serial Data In (EEDI) — WO. Note that this bit represents “Data In” from the perspective
2 of the EEPROM device. The value of this bit is written to the EEPROM when performing write
operations.
EEPROM Chip Select (EECS) — R/W.
1 0 = Drives the ICH6’s EE_CS signal low to disable the EEPROM. this bit must be set to 0 for a
minimum of 1 µs between consecutive instruction cycles.
1 = Drives the ICH6’s EE_CS signal high, to enable the EEPROM.
EEPROM Serial Clock (EESK) — R/W. Toggling this bit clocks data into or out of the EEPROM.
Software must ensure that this bit is toggled at a rate that meets the EEPROM component’s
0 minimum clock frequency specification.
0 = Drives the ICH6’s EE_SHCLK signal low.
1 = Drives the ICH6’s EE_SHCLK signal high.
Intel® I/O Controller Hub 6 (ICH6) Family Datasheet
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