82801FB Datasheet, PDF (400/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.1.6
BM_BREAK_EN Register (PM—D31:F0) (Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
ABh
00h
No
Core
Attribute:
Size:
Usage:
R/W
8-bit
ACPI, Legacy
Bit
Description
IDE_BREAK_EN — R/W.
0 = Parallel IDE or Serial ATA traffic will not act as a break event.
7 _{1 = Parallel IDE or Serial ATA traffic acts as a break event, even if the BM_STS-ZERO_EN and}
POPUP_EN bits are set. Parallel IDE or Serial ATA master activity will cause BM_STS to be set
and will cause a break from C3/C4.
PCIE_BREAK_EN — R/W.
0 = PCI Express* traffic will not act as a break event.
6 _{1 = PCI Express traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits}
are set. PCI Express master activity will cause BM_STS to be set and will cause a break from
C3/C4.
PCI_BREAK_EN — R/W.
5 ^{0 = PCI traffic will not act as a break event.}
1 = PCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are set.
PCI master activity will cause BM_STS to be set and will cause a break from C3/C4.
4:3 Reserved
EHCI_BREAK_EN — R/W.
2 ^{0 = EHCI traffic will not act as a break event.}
1 = EHCI traffic acts as a break event, even if the BM_STS-ZERO_EN and POPUP_EN bits are
set. EHCI master activity will cause BM_STS to be set and will cause a break from C3/C4.
UHCI_BREAK_EN — R/W.
0 = UHCI traffic will not act as a break event.
1 _{1 = USB traffic from any of the internal UHCIs acts as a break event, even if the BM_STS-}
ZERO_EN and POPUP_EN bits are set. UHCI master activity will cause BM_STS to be set and
will cause a break from C3/C4.
ACAZ_BREAK_EN — R/W.
0 = AC ‘97 or Intel High Definition Audio traffic will not act as a break event.
0 ^{1 = AC ‘97 or Intel High Definition Audio traffic acts as a break event, even if the BM_STS-}
ZERO_EN and POPUP_EN bits are set. AC ‘97 or
Intel High Definition Audio master activity will cause BM_STS to be set and will cause a break
from C3/C4.
400
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet