82801FB Datasheet, PDF (647/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.1.43
VCiCTL—VCi Resource Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 120h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31
30:27
26:24
23:20
19:17
16
15:8
7:0
VCi Enable — R/W.
0 = VCi is disabled
1 = VCi is enabled
Note: This bit is not reset on D3_HOT to D0 transition; however, it is reset by PLTRST#.
Reserved.
VCi ID — R/W. This field assigns a VC ID to the VCi resource. This field is not used by the ICH6
hardware, but it is R/W to avoid confusing software.
Reserved.
Port Arbitration Select — RO. Hardwired to 0 since this field is not valid for endpoint devices
Load Port Arbitration Table — RO. Hardwired to 0 since this field is not valid for endpoint devices
Reserved.
TC/VCi Map — R/W, RO. This field indicates the TCs that are mapped to the VCi resource. Bit 0 is
hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1] are implemented as R/W bits.
This field is not used by the ICH6 hardware, but it is R/W to avoid confusing software.
18.1.44
VCiSTS—VCi Resource Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 126h
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:2 Reserved.
1 VCi Negotiation Pending — RO. Does not apply. Hardwired to 0.
0 Port Arbitration Table Status — RO. Hardwired to 0 since this field is not valid for endpoint devices.
18.1.45
RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register (Intel^® High Definition Audio
Controller—D27:F0)
Address Offset: 130h
Default Value: 00010005h
Attribute:
Size:
RO
32 bits
Bit
Description
31:20 Next Capability Offset — RO. Hardwired to 0 indicating this is the last capability.
19:16 Capability Version — RO. Hardwired to 1h.
15:0 PCI Express* Extended Capability ID — RO. Hardwired to 0005h.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
647