82801FB Datasheet, PDF (394/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
A0h
0000h
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO, R/WO
16-bit
ACPI, Legacy
Core
Bit
15:11
10
9
8
7
(Desktop
Only)
7
(Mobile
Only)
6
5
4
3:2
(Desktop
Only)
3
(Mobile
Only)
2
(Mobile
Only)
1:0
Description
Reserved
BIOS_PCI_EXP_EN — R/W. This bit acts as a global enable for the SCI associated with the PCI
Express* ports.
0 = The various PCI Express ports and (G)MCH cannot cause the PCI_EXP_STS bit to go
active.
1 = The various PCI Express ports and (G)MCH can cause the PCI_EXP_STS bit to go active.
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Reserved
Reserved
Enter C4 When C3 Invoked (C4onC3_EN) — R/W. If this bit is set, then when software does a
LVL3 read, the ICH6 transitions to the C4 state.
i64_EN. Software sets this bit to indicate that the processor is an IA_64 processor, not an IA_32
processor. This may be used in various state machines where there are behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the processor
power.
NOTE: CPUSLP# will go active during Intel SpeedStep^® technology transitions and on entry to
C3 and C4 states even if this bit is not set.
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0)
will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect
(i.e., once set, this bit can only be cleared by PLTRST#).
Reserved
Intel SpeedStep Enable (SS_EN) — R/W.
0 = Intel SpeedStep technology logic is disabled and the SS_CNT register will not be visible
(reads to SS_CNT will return 00h and writes will have no effect).
1 = Intel SpeedStep technology logic is enabled.
PCI CLKRUN# Enable (CLKRUN_EN) — R/W.
0 = Disable. ICH6 drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock via the CLKRUN# and STP_PCI#
signals.
NOTE: when the SLP_EN# bit is set, the ICH6 drives the CLKRUN# signal low regardless of the
state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks continue
running during a transition to a sleep state.
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate at
which periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
394
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet