82801FB Datasheet, PDF (415/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
Bit
Description
RI_EN — R/W. The value of this bit will be maintained through a G3 state and is not affected by a
hard reset caused by a CF9h write.
8
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7
Reserved
TCOSCI_EN — R/W.
6
0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
AC97_EN — R/W.
0 = Disable.
5
1 = Enables the setting of the AC97_STS to generate a wake event.
NOTE: This bit is also used for Intel High Definition Audio when the Intel High Definition Audio
host controller is enabled rather than the AC97 host controller.
USB2_EN — R/W.
4
0 = Disable.
1 = Enables the setting of the USB2_STS to generate a wake event.
USB1_EN — R/W.
3
0 = Disable.
1 = Enables the setting of the USB1_STS to generate a wake event.
THRM#_POL — R/W. This bit controls the polarity of the THRM# pin needed to set the
THRM_STS bit.
2
0 = Low value on the THRM# signal will set the THRM_STS bit.
1 = HIGH value on the THRM# signal will set the THRM_STS bit.
HOT_PLUG_EN — R/W.
1
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1 = Enables the ICH6 to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow
the PCI Express ports to cause an SCI due to hot-plug events.
THRM_EN — R/W.
0
0 = Disable.
1 = Active assertion of the THRM# signal (as defined by the THRM_POL bit) will set the
THRM_STS bit and generate a power management event (SCI or SMI).
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
415